Do I Need Separate Clock For Shift Register With Loads?

Lab 4: Shift Registers

one.     Introduction

A shift register is an n-bit register with provision for shifting its stored data past one position at each clock pulse.  The logical configuration of a shift annals consists of a chain of flip-flops connected in cascade, with the output of one flip-flop continued to the input of the side by side flip-flop.  All flip-flops receive a common clock pulse which causes the shift from one stage to the side by side.  Fig. 1 shows a unproblematic shift annals configuration.  The new bit to exist shifted into one cease must exist specified, and the bit shifted off the other stop is lost unless it is saved externally.  Although Fig. one shows a right-shift register, the same register can obviously exist used for left shifts but by reversing the sense of the bits.  Nearly shift registers have provision for shifting only in ane direction, only some accept a control input that allows either left or right shifting to be specified at each clock.

Fig. 1. 4-fleck shift register.

One way to load n bits of data into the flip-flop chain is to load the data one scrap each clock cycle using the serial input.  Some shift registers also have parallel inputs that can exist used to load all n $.25 in one clock cycle.  The output of a shift register can be observed i scrap at a fourth dimension at the series output, but some shift registers as well have parallel outputs for observing all n bits at once.

Shift registers are classified according to 3 basic considerations: their method of data handling (series-in series-out, serial-in parallel-out, and parallel-in serial-out), their direction of information movement (shift right, shift left, and bidirectional), and their bit length.  Ane of the important applications of shift register circuits is in serial computation.  Compared to parallel computation, where all bits in a give-and-take are candy at the same cycle, series computation process words in one bit per cycle.  Therefore, serial computation is slower, merely it has the advantage of requiring less hardware and wiring.  A serial adder will exist built in this experiment as an case.

2.     Objectives

Students are expected to empathise diverse information treatment methods in shift registers and their usage.

3.     Experiment

3.1.   4-bit Shift Register

Use two 7474 dual flip-flops to connect a series-in, parallel-out shift annals every bit shown in Fig. 1.  Connect L1–L4 to iv LEDs (with current-limiting resistors), SW1 and SW2 to switches, and CLK to a pulser. Initially, set SW2 to logic 1.  Switch SW2 being at logic one clears all flip-flops.  Now prepare SW1 to logic 1 and SW2 to logic 0.  Push the pulser button several times to permit more logic ane to exist shifted into the shift register.  Change SW1 to logic 0 and echo the experiment again.

3.2.   Pseudo-random Sequence Generator

Now use the above circuit to build a pseudo-random binary sequence generator as shown in Fig. 2. This binary sequence generator will display a random output (repeats every 2ⁿ–1 bits, where northward is the number of flip-flops used in the shift register). The IC 7486 provides the exclusive-OR needed in the circuit. To start the sequence generator, fix the initial state of the shift register to 0001 by setting the switch SW1 to logic 1. Then change SW1 to logic 0 as this will release the command input. At present apply the clock and record the output in a table. Does the output show randomness? Does the output echo after 15 pulses?

Fig. 2. Pseudo-random binary sequence generator.

3.three.    Serial Adder

A serial adder adds bits adds a pair of binary numbers serially with a elementary full adder.  The carry out of the full adder is transferred into a D flip-bomb and the output of this carry flip-flop is and then used as the input comport for the next pair of meaning bits.  Fig. three illustrates an example of serial addition.

Fig. three Serial add-on.

Fig. 4. shows the cake diagram design of a serial adder.  The ii binary numbers to be added serially are stored in 2 shift registers (using two 74164, 8-bit serial-in, parallel-out shift registers).  Bits are added one pair at a time through a single full adder (such as the one in Experiment two)  The carry out of the full adder is transferred into a D flip-bomb. The output of this carry flip-flop is and so used equally the input comport for the adjacent pair of significant bits.  The sum output from the full adder is transferred into register A every bit the contents of the annals are shifted out.

To perform the add-on, the following steps are used.

1. Shift the first eight-chip augend into A (recall to shift in LSB first) and addend into B. This is washed by performing the following steps:

1. Articulate registers A and B, and the D flip-flop.  The registers and flip-flop have a clear input that tin be used to accomplish this task.


2. Shift the augend through the serial input.  For 8-scrap registers, i bit volition be shifted into register B for each of 8 clock cycles, least significant bit first.  (Since registers A and B initially comprise all zeroes, the output of the full adder volition be 0 for both the sum and conduct outputs during these clock cycles.  Y'all can either load these zeroes into annals A or just leave A unchanged.  In either case, subsequently viii clock cycles, Register B will contain one operand and register A will incorporate all zeroes.


3. Shift the addend through the serial input.  This is actually two tasks performed at once.  While the addend is beingness shifted into annals B, the augend is being shifted out of B and into register A.  To understand how this occurs, recall that annals A contains all zeroes.  Whatever bit is being shifted out of B is being added to the nil in the least pregnant flake of A.  The sum will simply be the to the lowest degree significant bit of B, which is shifted into the most significant position of annals A.  After eight clock cycles, register A contains the augend and register B contains the addend.

2. Articulate the D flip-flop and run the adder for eight cycles to obtain the sum.

Fig. iv. Block diagram of a serial adder.

Tabular array i shows the values in registers A and B when the data values 01011101 and 10011110 are added together.

Table ane: Trace of the serial adder
Serial Input	Annals A	Annals B	D FF	Comments
X	00000000	00000000	0	Clear A, B, D
1	00000000	10000000	0
0	00000000	01000000	0
i	00000000	10100000	0
1	00000000	11010000	0
1	00000000	11101000	0
0	00000000	01110100	0
ane	00000000	10111010	0
0	00000000	01011101	0	Augend in B; 0 in A
0	10000000	00101110	0	0+1=1
1	01000000	10010111	0
ane	10100000	11001011	0
1	11010000	11100101	0
1	11101000	11110010	0
0	01110100	01111001	0
0	10111010	00111100	0
i	01011101	10011110	0	Augend in A; Addend in B
Ten	10101110	X1001111	0	C=0, S=1
X	11010111	XX100111	0	C=0, S=1
X	01101011	XXX10011	ane	C=1, South=0
10	10110101	XXXX1001	1	C=1, S=1
Ten	11011010	XXXXX100	1	C=ane, Southward=1
Ten	11101101	XXXXXX10	0	C=0, S=1
X	11110110	XXXXXXX1	0	C=0, Due south=1
Ten	11111011	XXXXXXXX	0	Sum in A

4.     Prelab

1. Bear witness the sequence generated by the pseudo-random sequence generator.
2. Study the operation of the 74164.
3. Draw a excursion diagram of the series adder showing the connections for all the components.
4. What is the maximum clock speed for the adder excursion of part 3.three? Presume worst case delays and 74LSXX type logic.

5.     Equipment and parts required.

• Protoboard
• Two TTL D Flip-Flops (7474)
• One TTL NAND (7400)
• One TTL inverter (7404)
• Ane TTL XOR (7486)
• Two TTL Shift registers (74164)
• Eight LEDs and limiting resistors

Do I Need Separate Clock For Shift Register With Loads?,

Source: http://ecelabs.njit.edu/ece394/lab4.php

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